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Technical support Email
support@cellwise-semi.com
Management team
Bob JIANG (GM)
Ex-Design Service Manager of Synopsys, manage over 40 chips design and tape out for IC industry, all 1st silicon success.

WG GE (CTO)
Mr. GE has professional experience in Analog/Mixed Signal ASIC design, ex-Design Director of ST PMU BU, managed over 100 power and battery related IC designs for ST. Inventor of 4 U.S. patents.

JH ZHAO (VP of RD)
Mr. ZHAO has professional experience in  Analog/Mixed Signal ASIC design, ex-Design Manager of ST AAL BU, his design generate over 1Billion revenue for ST. Inventor of 8 U.S. patents.
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